The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that reduces the likelihood of localized breakthrough in the thin gate oxidation near the edges of a poly-silicon or amorphous-silicon gate stack.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (NOS) transistors, such as P-channel MOS (PMOS), N-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistor, an active device generally includes a source and drain region and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacturing of such devices is the formation of devices, or portions thereof, using photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. Next, the wafer is exposed to light; the light striking the wafer is passed through a mask plate. This mask plate defines the desired features to be printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photoresist-coated substrate. Unexposed areas of resist are washed away. The wafer having the desired features defined is subjected to etching. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma. A challenge in the etching process is maintaining control over the etching of the features, notably in the gate electrode region of the MOS transistor.
One of the challenges during the gate etch process of sub-micron technologies is the control of the etch profile. In many modern sub-micron processes, the gate electrode is comprised of a composite of layers of materials xe2x80x9cstackedxe2x80x9d on top of one another, hence the name, xe2x80x9cgate stack.xe2x80x9d In an example process, a CMOS transistor with a gate stack comprising 1000 xc3x85 of W, 500 xc3x85 of TiN provides a sheet resistance as low as 3xcexa9/xe2x96xa1 and a higher breakdown voltage for the gate oxide.
A commonly used gate stack is amorphous silicon (xcex1-Si) or poly silicon (poly-Si) on top of a thin gate oxide. The xcex1-Si or poly-Si is typically doped with N-type carriers for NMOS or with P-type carriers for PMOS to obtain asymmetry threshold voltage between N-channel and P-channel devices for a CMOS device. As the technologies evolve, the dimensions of integrated circuits shrink. As the IC dimensions get smaller, a thinner gate oxide is needed to maintain a level of gate capacitance for the performance of the IC devices. To avoid increasing the capacitance above the desired level, it is necessary to maintain a high conductivity in the xcex1-Si or poly-Si to prevent the depletion of carriers in the gate region. This depletion of carriers tends to make the xcex1-Si or poly-Si appear as an additional xe2x80x9coxide thicknessxe2x80x9d contributing series capacitance component that tends to lower the overall gate capacitance. For an example process having 100 xc3x85 oxide, if the gate stack contributes 5 xc3x85 of xe2x80x9coxide thicknessxe2x80x9d, the capacitance change would be about 5% (assuming other parameters are held constant). However, if a process has a 30 xc3x85 gate, with a 5 xc3x85 change in thickness due to the oxide, the gate capacitance would change about 20%. Therefore, the N-type and P-type doses required for the xcex1-Si or poly-Si gate stack may be heavier. The thinning of the gate oxidation and the doping heavily of the xcex1-Si and poly-Si with N-type or P-type carriers present a major challenge to the gate etch process.
Different doping types, doses, and activation level of the xcex1-Si or poly-Si have a significant effect on the xcex1-Si or poly-Si etch rate as well as the etch profile. N-doped xcex1-Si or poly-Si usually etches faster than P-doped xcex1-Si or poly-Si in a plasma etch process. To adequately etch the P-type material there is a possibility of etching the N-type material too much. The excessive etching may cause the localized breakthrough, xe2x80x9cmicro-trenching,xe2x80x9d of the thin gate oxidation in the bottom of the xcex1-Si or poly-Si etch features.
In a typical xcex1-Si or poly-Si gate plasma etching process, a main-etch step with an optical endpoint is used to define the gate profile. The endpoint signal will trigger only when the xcex1-Si or poly-Si begins clearing out of the wafer. At this point, there will be less N-doped xcex1-Si remaining than P-doped Si. Some N-doped xcex1-Si may have been completely etched away. The etch process will break through the thin gate oxide and rapidly etch the underlying silicon substrate. After reaching the endpoint (or after the main-etch step) the process switches to a higher Si/SiO2 selectivity over-etch step and completely removes all of the remaining xcex1-Si (or poly-Si). The selectivity of the over-etch step is much more than that of the main-etch step. This assures a reasonable gate profile.
With a relatively thin gate oxide, micro-trenching is problematic, especially in N-doped areas. In a plasma etch process, gate etch profile is also very sensitive to the doping of xcex1-Si or poly-Si. In addition, the doping profiles between N-doped and P-doped xcex1-Si or poly-Si may be different especially for dense xcex1-Si or poly-Si lines.
Accordingly, there is a need to maintain a good gate etch profile that is substantially free of micro-trenching and provides a consistent gate etch profile between N-type and P-type doped gate stacks as well as good critical dimension control as the process technology is approaching fractional microns in feature sizes.
The present invention is exemplified in a number of implementations, several of which are summarized below. According to one embodiment, a method for building a gate structure over a thin oxide region in a semiconductor device having a silicon region of a first polarity type comprises forming a layer of undoped silicon coupled to and over the thin oxide region. At least one gate region on the undoped silicon is defined on the thin oxide region. The thin oxide region is over the silicon region of a first polarity type. A drain and source region of a second polarity type is defined. Next, a dielectric layer over the gate region is then formed. The layer of undoped silicon coupled to the thin oxide region is transformed into silicon of a second polarity type.
According to another embodiment, a CMOS device structure has P-well and N-well regions, trench isolation regions separating the wells and other device structures, and a thin oxide region. A method for building a CMOS gate stack structure comprises first forming a layer of undoped silicon coupled to and over the thin oxide region. Second, a layer of undoped silicon coupled to the thin oxide regions is formed. Third, at least one gate region on the undoped silicon is defined on the thin oxide over the P-well and at least one gate region on the undoped silicon is formed on the thin oxide over the N-well regions in the device structure. The source and drain regions of the device structure then undergo ion implant. Next, a dielectric layer is deposited onto the gate region, and this dielectric region is planarized until the top surface of the gate region is exposed. The undoped silicon in the P-well is implanted to form an N-type stack. In addition, the undoped silicon of the N-well is implanted to form a P-type stack. The dielectric layer is removed until the thin oxide region is exposed and spacers are formed around the N-type gate stack and P-type gate stack.
The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows.